1. Field of the Invention
The invention relates to direct memory access (DMA) controllers, and more particularly, to an improved DMA controller having programmable timing.
2. Description of the Related Art
To improve overall computer system performance, computer systems today include a direct memory access or DMA controller to enable I/O devices to access main memory without the intervention of the CPU. In computer systems according to the Industry Standard Architecture (ISA) or Extended Industry Standard Architecture (EISA), two 8237 DMA controllers from Intel Corporation are utilized, or in the alternative, an 8237-compatible DMA controller can be used.
The DMA controller in the ISA computer system supports either 8 or 16-bit I/O devices, while the DMA controller in the EISA system further supports 32-bit I/O devices. The DMA controller in an ISA or EISA system provides seven DMA channels, each channel capable of being programmed for several different transfer modes and timing modes. A DMA channel can operate in one of four transfer modes, which include the single transfer, block transfer, demand transfer, or cascade modes. In single transfer mode, a DMA channel performs only one data transfer for each arbitration cycle. In block transfer mode, a predetermined block of data is transferred in each arbitration cycle. In demand transfer mode, the DMA controller has the capability of continuing the data transfer until the I/O device has exhausted its data capacity. Finally, each channel of the DMA controller can also be programmed to cascade mode.
One application of cascade mode is where two 8237 devices are cascaded together. As each 8237 DMA controller includes only four DMA channels, cascading is required to obtain the seven channels. Thus, one of the channels of the first level 8237 DMA controller is programmed in cascade mode and connected to a second level 8237 DMA controller. This allows the DMA requests of the second level device to propagate through the priority network circuitry of the first level device. Thus, the cascade channel of the first level DMA controller is used only for prioritizing the second level device, and it does not output any address or control signals of its own as that would conflict with the output signals of the active channel in the second level device.
Another application of programming a channel to cascade mode is to allow an I/O device on the expansion bus to use a DMA channel for bus requests. Thus, instead of requiring the use of a separate arbiter to arbitrate between the I/O devices, the prioritization scheme between the DMA channels can be used to process requests from the I/O devices. When thus programmed, the DMA channel does not perform data transfers to a memory slave. Instead, the output signals of the DMA channel are disabled to allow the I/O device to gain control of the bus. For more detailed information on the various transfer modes of the 8237 DMA controller, refer to Peripheral Components, Intel Corp., pgs. 5-4 to 5-21 (1994), which is hereby incorporated by reference.
The 8237 type DMA controllers also use one of four timing modes: ISA compatible cycles, Type A cycles, Type B cycles and Type C or burst DMA cycles. It is noted that all the timing modes can be used when the DMA controller is programmed in the single transfer mode. However, if the 8237 DMA controller is programmed in either the block transfer mode or the demand transfer mode, then the ISA compatible timing mode cannot be used as there exists the possibility that other devices, including the refresh controller, can be locked out.
In ISA compatible timing mode, one DMA transfer is performed in eight BCLK or ISA bus clocks. In the Type A timing mode, a DMA transfer can be completed in six BCLK periods. Type B timing provides better performance than Type A timing, as it supports DMA transfers that can be executed every four BCLK periods. Both Type A and Type B timings require the use of fast memory devices. When programmed in burst DMA or Type C timing mode, the DMA cycles have characteristics that are similar to burst cycles. Thus, transfers can be performed between the memory slave device and the DMA device in one BCLK period each.
As can be seen from the discussion above, the 8237-type DMA controller provides for a number of different timing modes to compensate for different timing requirements of different components in a computer system. Thus, if a computer system is implemented with a fast memory device, then the faster DMA timing modes can be utilized. However, there are also a multitude of I/O devices each having different functional and timing requirements. It has been determined that the four timing modes provided by the 8237 DMA controller do not provide sufficient flexibility to optimize DMA performance for the timing requirements of the different I/O devices. Therefore, it is desired that a more flexible and improved DMA controller be provided.